Apparatus and method for improving or optimizing buffer size in dual connectivity

ABSTRACT

A device for wireless communication of user equipment (UE) in a dual connection system includes a memory providing a buffer storing first data received from a first base station (BS) and second data received from a second BS and a first processor generating a radio bearer (RB) by reordering the first data and the second data and adjusting a size of the buffer based on a delay between the first BS and the second BS.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based on and claims priority under 35 U. S. C. § 119to Korean Patent Application No. 10-2020-0108540, filed on Aug. 27,2020, in the Korean Intellectual Property Office, the disclosure ofwhich is incorporated by reference herein in its entirety.

BACKGROUND

The inventive concepts relate to wireless communication, and moreparticularly, to an apparatus and a method for improving or optimizing abuffer size in dual connectivity (DC).

In the wireless communication, in order to increase throughput, varioustechniques may be adopted. For example, DC may be formed between aterminal and two or more base stations (BSs). DC may imply that theterminal consumes radio resources provided by the two or more BSs. Datasplit by one BS may be transmitted to the terminal through the two ormore BSs and data split by the terminal may be transmitted to the two ormore BSs and may be put together in one BS. The two or more BSs may beconnected through a non-ideal backhaul interface. Therefore, it may beadvantageous to more efficiently process a delay caused by an interfacebetween BSs, in the DC.

SUMMARY

The inventive concepts relate to an apparatus and a method for moreefficiently using a buffer based on a delay of an interface between basestations (BSs).

According to an aspect of the inventive concepts, there is provided adevice for wireless communication of user equipment (UE) in a dualconnection system, the device including a memory providing a bufferstoring first data received from a first BS and second data receivedfrom a second BS and a first processor generating a radio bearer (RB) byreordering the first data and the second data and adjusting a size ofthe buffer based on a delay between the first BS and the second BS.

According to an aspect of the inventive concepts, there is provided amethod for wireless communication of UE in a dual connection system, themethod including storing first data received from a first BS and seconddata received from a second BS in a first region in a memory, the firstregion being allocated to a buffer, generating a RB by reordering thefirst data and the second data, and adjusting a size of the first regionbased on a delay between the first BS and the second BS.

According to an aspect of the inventive concepts, there is provided amethod performed by a first base station (BS) for wirelesscommunication, the method including forming dual connectivity (DC) witha second BS and UE, identifying a delay between the first BS and thesecond BS, and transmitting a measured value corresponding to theidentified delay to the UE.

BRIEF DESCRIPTION OF THE DRAWINGS

Example embodiments of the inventive concepts will be more clearlyunderstood from the following detailed description taken in conjunctionwith the accompanying drawings in which:

FIG. 1 is a view illustrating a wireless communication system accordingto example embodiments of the inventive concepts;

FIG. 2 is a block diagram illustrating an example of a protocol stackaccording to example embodiments of the inventive concepts;

FIG. 3 is a timing diagram illustrating an example of packet dataconvergence protocol (PDCP) packet data units (PDUs) received by a PDCPentity in dual connectivity (DC) according to example embodiments of theinventive concepts;

FIGS. 4A and 4B are block diagrams illustrating examples of a wirelesscommunication system according to example embodiments of the inventiveconcepts;

FIGS. 5A and 5B are timing diagrams illustrating examples of a bufferingoperation performed by user equipment (UE) for data reordering inaccordance with comparative examples;

FIG. 6 is a block diagram illustrating base stations (BS) and UE in DCaccording to example embodiments of the inventive concepts;

FIG. 7 is a flowchart illustrating a method of improving or optimizing abuffer size in DC according to example embodiments of the inventiveconcepts;

FIG. 8 is a timing diagram illustrating an example of a bufferingoperation performed by UE for data reordering according to exampleembodiments of the inventive concepts;

FIGS. 9A and 9B are flowcharts illustrating examples of a method ofimproving or optimizing a buffer size in DC according to exampleembodiments of the inventive concepts;

FIGS. 10A and 10B are flowcharts illustrating examples of a method ofimproving or optimizing a buffer size in DC according to exampleembodiments of the inventive concepts;

FIG. 11 is a view illustrating a radio access network (RAN) according toexample embodiments of the inventive concepts; and

FIGS. 12A and 12B are block diagrams illustrating examples of devicesfor wireless communication according to example embodiments of theinventive concepts.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

FIG. 1 is a view illustrating a wireless communication system accordingto example embodiments of the inventive concepts. For example, FIG. 1illustrates a radio access network (RAN) and a core network 30. Forexample, the RAN may include an evolved UMTS terrestrial RAN (E-UTRAN)based on radio access technology (RAT) of long term evolution (LTE) orLTE-advanced (LTE-A) and the core network 30 may include an evolvedpacket core (EPC) so that an evolved packet system (EPS) may beimplemented. In addition, the RAN may include a next generation (NG)-RANbased on a 5^(th) generation (5G) new radio (NR) RAT and the corenetwork 30 may include a 5G core (5GC) so that a 5G system (5GS) may beimplemented.

A first or second base station (BS) 21 or 22 may generally refer to afixed station communicating with user equipment (UE) 10 and another BSand may exchange data and control information by communicating with theUE 10 and/or another BS. For example, the first or second BS 21 or 22may be referred to as a node B, an evolved-node B (eNB), a nextgeneration node B (gNB), a sector, a site, a base transceiver system(BTS), an access point (AP), a relay node, a remote radio head (RRH), aradio unit (RU), or a small cell. In addition, the first or second BS 21or 22 may be referred to as an ng-eNB that is an eNB interlockable withthe 5GC and the gNB or an en-gNB interlockable with the EPC and the eNB.Herein, the first or second BS 21 or 22 or a cell may be interpreted ascomprehensive meaning representing a partial area or function covered bya base station controller (BSC) in code division multiple access (CDMA),the node B in wideband code division multiple access (WCDMA), the eNB inLTE, or the gNB or the sector (the site) in 5G and may encompass variouscoverage areas such as a megacell, a macrocell, a microcell, a picocell,a femtocell, a relay node, the RRH, the RU, and a small cellcommunication range.

The UE 10 may refer to arbitrary devices that may be fixed or movableand that may communicate with the first or second BS 21 or 22 and maytransmit and receive the data and/or the control information. Forexample, the UE 10 may be referred to as a terminal, terminal equipment,a mobile station (MS), a mobile terminal (MT), a user terminal (UT), asubscriber station (SS), a wireless device, or a handheld device. Inaddition, the UE 10 may refer to a vehicle in vehicle-to-everything(V2X).

Referring to FIG. 1, the UE 10 may be connected to the first BS 21 andthe second BS 22 through a Uu interface. The RAN between the UE 10 andthe first or second BS 21 or 22 may support communications among aplurality of users by sharing available network resources. For example,the RAN may adopt multiple access technology such as CDMA, frequencydivision multiple access (FDMA), time division multiple access (TDMA),orthogonal frequency division multiple access (OFDMA), single carrierfrequency division multiple access (SC-FDMA), orthogonal frequencydivision multiplexing-frequency division multiple access (OFDM-FDMA),OFDM-TDMA, or OFDM-CDMA as a non-limiting example. The first BS 21 andthe second BS 22 may be connected to each other through a non-idealbackhaul interface, for example, through an X2/Xn interface asillustrated in FIG. 1.

The UE 10 may form dual connectivity (DC) with the first BS 21 and thesecond BS 22. The DC may indicate that radio resources provided by twoor more BSs are consumed by one UE 10. In the DC, one BS may be referredto as a master node (MN) and the other BS may be referred to as asecondary node (SN). Herein, it is assumed that the first BS 21 is theMN and the second BS 22 is the SN.

In the DC, the UE 10 and the first BS 21 and/or the second BS 22 mayexperience an inter-BS delay, that is, a delay caused by the X2/Xninterface between the first BS 21 and the second BS 22. For example, indownlink (DL) data transmission, when first data is transmitted from thefirst BS 21 to the UE 10 through the Uu interface and second data istransmitted from the first BS 21 to the UE 10 through the X2/Xninterface, the second BS 22, and the Uu interface, the UE 10 may receivethe second data delayed due to the X2/Xn interface. At this time, thedelay experienced by the UE 10 may include the delay of the X2/Xninterface and queuing delay in the second BS 22. Herein, the delayexperienced by the UE 10 in the DC may be referred to as an inter-BSdelay, the delay between the BSs or the delay caused by the X2/Xninterface or may be simply referred to as delay.

Like in the DL data transmission, in uplink (UL) data transmission, whenthe first data is transmitted from the UE 10 to the first BS 21 throughthe Uu interface and the second data is transmitted from the UE 10 tothe first BS 21 through the Uu interface, the second BS 22, and theX2/Xn interface, the first BS 21 may receive the second data delayed dueto the X2/Xn interface. Therefore, the UE 10 or the first BS 21 mayreceive data out-of-sequence.

Each of the UE 10 and the first BS 21 and/or the second BS 22 mayinclude a buffer for reordering data received out-of-sequence throughdifferent paths in the DC as described below with reference to FIG. 2.For example, in the DL data transmission, the UE 10 may generate a radiobearer (RB) by reordering the first data received from the first BS 21and the second data received from the second BS 22 and may include abuffer storing the first data and/or the second data in order to reorderthe first data and the second data. Likewise, in the UL datatransmission, the first BS 21 may generate the RB by reordering thefirst data received from the UE 10 and the second data received from thesecond BS 22 and may include a buffer storing the first data and/or thesecond data in order to reorder the first data and the second data.

The RAT may regulate a total buffer size for reordering data in the UE10, and the UE 10 may be required to include memory providing the totalbuffer size. For example, Document 1 “3GPP TS 38.306, NR; User Equipment(UE) radio access capabilities (Release 16)” regulates the UE 10 toprovide a buffer of a size defined in the following [EQUATION 1] and[EQUATION 2] for DL data transmission.

MaxDLDataRate_SN×RLCRTT_SN+MaxDLDataRate_MN×(RLCRTT_SN+X2/Xndelay+Queuing in SN)  [EQUATION 1]

MaxDLDataRate_MN×RLCRTT_MN+MaxDLDataRate_SN×(RLCRTT_MN+X2/Xndelay+Queuing in MN)  [EQUATION 2]

[EQUATION 1] may correspond to a case in which a bearer split from theSN is generated, and [EQUATION 2] may correspond to a case in which abearer split from the MN is generated. In [EQUATION 1] and [EQUATION 2],MaxDLDataRate_MN represents the maximum DL data speed of the MN,MaxDLDataRate_SN represents the maximum DL data speed of the SN,RLCRTT_MN represents an radio link control (RLC) retransmission timefrom the MN to the UE 10, RLCRTT_SN represents an RLC retransmissiontime from the SN to the UE 10, X2/Xn delay represents a delay generatedby the X2/Xn interface between the MN and the SN, Queuing in SNrepresents a time spent on queuing in the SN, and Queuing in MNrepresents a time spent on queuing in the MN.

In the DC, various scenarios may be generated and, as a memory regionhaving a size less than the above-described total buffer size is used inaccordance with a scenario, the memory region may be wasted.Hereinafter, as described below with reference to the drawings, in theDC, a size of a buffer used for reordering data may be improved oroptimized based on the inter-BS delay, that is, the delay caused by theX2/Xn interface. Therefore, a memory region, which is secured due to theimproved or optimized buffer size, may be reused and performances of theUE 10 and the first BS 21 and/or the second BS 22 may improve. Inaddition, due to the improved or optimized buffer size, memory capacitymay be reduced and costs of the UE 10 and the first BS 21 and/or thesecond BS 22 may be reduced.

FIG. 2 is a block diagram illustrating an example of a protocol stackaccording to example embodiments of the inventive concepts. For example,the block diagram of FIG. 2 illustrates a part of a radio protocolarchitecture for a user plane during the DL data transmission in the DCformed by UE 100 with a first BS 210 and a second BS 220.

The first BS 210, the second BS 220, and the UE 100 may communicate withone another based on lower three layers, that is, a first layer L1, asecond layer L2, and a third layer L3 of an open system interconnection(OSI) reference model. For example, as illustrated in FIG. 2, the firstBS 210, the second BS 220, and the UE 100 may communicate with oneanother based on a physical (PHY) layer included in the first layer L1and a medium access control (MAC) layer, a radio link control (RLC)layer, and a packet data convergence protocol (PDCP) layer included inthe second layer L2. In addition, although not shown in FIG. 2, thefirst BS 210, the second BS 220, and the UE 100 may communicate with oneanother based on a radio resource control (RRC) layer and a non-accessstratum (NAS) layer of a control plane included in the third layer L3.As illustrated in FIG. 2, the PHY layer may provide an informationtransfer service to an upper layer by using a physical channel and maybe connected to the MAC layer through a transmission channel. Inaddition, the MAC layer may be connected to the RLC layer through alogic channel, the RLC layer may be connected to the PDCP layer throughan RLC channel, and the PDCP layer may be connected to an upper layerthrough the RB.

The PDCP layer may perform transmission of user data, headercompression, and ciphering. The RLC layer may perform concatenation,segmentation, and recombination of an RLC service data unit (SDU) andmay support various modes in order to guarantee quality of service (QoS)required by the RB. The MAC layer may perform mapping between the logicchannel and the transmission channel and multiplexing and demultiplexingbetween an MAC SDU and a transmission block. The PHY layer may transmitand receive information through the physical channel. For example, thephysical layer may transmit and receive information through a physicaldownlink control channel (PDCCH), a physical downlink shared channel(PDSCH), a physical control format indicator channel (PCFICH), aphysical hybrid ARQ indicator channel (PHICH), a physical uplink controlchannel (PUCCH), and a physical uplink shared channel (PUSCH).

The first BS 210 and the second BS 220 may include entities forperforming the layers, respectively. For example, as illustrated in FIG.2, the first BS 210 may include a PDCP entity 212, an RLC entity 214, anMAC entity 216, and/or a PHY entity 218. In addition, the second BS 220may include an RLC entity 224, an MAC entity 226, and/or a PHY entity228. The PDCP entity 212 of the first BS 210 may generate a PDCP packetdata unit (PDU) to which a PDCP header is added by performing headercompression and encryption on a PDCP SDU. The PDCP PDU may include aPDCP data PDU and a PDCP control PDU. The PDCP data PDU may carry userplane data and control plane data and PDCP SDU sequence numbers (SN) (orPDCP SNs). The PDCP control PDU may carry a PDCP status report andheader compression control information.

When a multi-flow is formed in the DC, the PDCP entity 212 of the firstBS 210 may split one RB so that a split bearer may be generated. Forexample, as illustrated in FIG. 2, the PDCP entity 212 may receive apacket corresponding to the RB and may generate PDCP PDUs from thereceived packet. The PDCP entity 212 may properly distribute and providethe PDCP PDUs to the RLC entity 214 of the first BS 210 and the RLCentity 224 of the second BS 220 based on a previously defined ruleand/or an arbitrary method. The PDCP entity 212 of the first BS 210 mayprovide the PDCP PDUs to the RLC entity 224 of the second BS 220 throughthe X2/Xn interface as described above with reference to FIG. 1. The RLCentities 214 and 224 of the first and second BSs 210 and 220 maygenerate RLC PDUs from the PDCP PDUs, that is, RLC SDUs. The RLC PDUsmay be transformed through the MAC entities 216 and 226 and the PHYentities 218 and 228 and may be transmitted to the UE 100.

The UE 100 may include a first RLC entity 114, a first MAC entity 116,and/or a first PHY entity 118 corresponding to the first BS 210 and mayinclude a second RLC entity 124, a second MAC entity 126 and/or a secondPHY entity 128 corresponding to the second BS 220. In addition, the UE100 may include a PDCP entity 112 commonly corresponding to the first BS210 and the second BS 220 and the PDCP entity 112 may receive the RLCSDUs, that is, the PDCP PDUs, from the first RLC entity 114 and thesecond RLC entity 124.

A delay occurring in a process of providing the PDCP PDU from the PDCPentity 212 of the first BS 210 to the RLC entity 224 of the second BS220, that is, the delay caused by the X2/Xn interface, may cause adifference (that is, a time difference) between a point in time at whichthe PDCP entity 112 of the UE 100 receives the PDCP PDUs (that may bereferred to as first data or first PDCP PDUs herein) from the first RLCentity 114 and a point in time at which the PDCP entity 112 of the UE100 receives the PDCP PDUs (that may be referred to as second data orsecond PDCP PDUs herein) from the second RLC entity 124. Therefore, asdescribed below with reference to FIG. 3, the PDCP PDUs may not beprovided to the PDCP entity 112 in the order of the PDCP SNs. The PDCPentity 112 of the UE 100 may be required to provide the PDCP SDUs to anupper layer in the order of the PDCP SNs. Therefore, the PDCP entity 112may reorder the PDCP PDUs provided by the first RLC entity 114 and thePDCP PDUs provided by the second RLC entity 124 in accordance with thePDCP SNs and the UE 100 may provide a buffer used for reordering thePDCP PDUs. Because the buffer is used in the second layer L2, the buffermay be referred to as a layer 2 buffer. Herein, the layer 2 buffer maybe simply referred to as a buffer.

The split bearer generated by the DL data transmission described abovewith reference to FIG. 2 may be similarly generated in the UL datatransmission. For example, when the multi-flow is formed in the DC, thePDCP entity 112 of the UE 100 may split one RB and may properlydistribute and provide the PDCP PDUs to the first RLC entity 114 and thesecond RLC entity 124. Therefore, the PDCP entity 212 of the first BS210 may receive the RLC SDUs, that is, the PDCP PDUs, from the RLCentity 214 of the first BS 210 and the RLC entity 224 of the second BS220. Like the PDCP entity 112 of the UE 100, the PDCP entity 212 of thefirst BS 210 may also reorder the PDCP PDUs. In order to reorder thePDCP PDUs, the first BS 210 may provide a buffer used for reordering thePDCP PDUs. For example, for a plurality of UEs forming dual connectivitycomponents related to the first BS 210, the first BS 210 may provide abuffer of a large size. Hereinafter, example embodiments of theinventive concepts will be described mainly with reference to the DLdata transmission. However, example embodiments of the inventiveconcepts may also be applied to the UL data transmission.

FIG. 3 is a timing diagram illustrating an example of PDCP PDUs receivedby a PDCP entity in dual connectivity (DC) according to exampleembodiments of the inventive concepts. As described above with referenceto FIG. 2, the PDCP entity 112 of the UE 100 may receive a first PDCPPDU PDCP_PDU1 from the first RLC entity 114 and may receive a secondPDCP PDU PDCP_PDU2 from the second RLC entity 124. Hereinafter, FIG. 3will be described with reference to FIG. 2.

Referring to FIG. 3, the PDCP entity 212 of the first BS 210 may providePDCP PDUs corresponding to PDCP SNs 1, 2, 3, 4, 5, 11, 12, 13, 17, 18,and 19 to the RLC entity 214 so that the corresponding PDCP PDUs may betransmitted to the UE 100 through the Uu interface between the first BS210 and the UE 100. In addition, the PDCP entity 212 of the first BS 210may provide PDCP PDUs corresponding to PDCP SNs 6, 7, 8, 9, and 10 tothe RLC entity 224 of the second BS 220 so that the corresponding PDCPPDUs may be transmitted to the UE 100 through the X2/Xn interfacebetween the first BS 210 and the second BS 220 and through the Uuinterface between the second BS 220 and the UE 100.

As illustrated in FIG. 3, the UE 100 (or the PDCP entity 112) mayreceive the PDCP PDU corresponding to the PDCP SN 1 from the first BS210 at a time t31 and may subsequently and sequentially receive the PDCPPDUs corresponding to the PDCP SNs 2, 3, 4, 5, 11, and 12. The UE 100(or the PDCP entity 112) may receive the PDCP PDU corresponding to thePDCP SN 6 from the second BS 220 at a time t32 and may subsequently andsequentially receive the PDCP PDUs corresponding to the PDCP SNs 7, 8,9, and 10. Therefore, the UE 100 may receive the PDCP PDU correspondingto the PDCP SN 6 at the time t32 delayed from the time t31 by D30 andthe delay D30 may be caused by the X2/Xn interface between the first BS210 and the second BS 220 so that the delay D30 may vary in accordancewith the BSs to which the UE 100 is connected.

The PDCP entity 112 of the UE 100 may reorder the PDCP PDUs. Forexample, the PDCP entity 112 of the UE 100 may provide the PDCP SDUsfrom the PDCP PDUs corresponding to the PDCP SNs 1, 2, 3, 4, and 5 to anupper layer and may store the PDCP PDUs corresponding to the PDCP SNs11, 12, 13, 17, 18, and 19 (or the PDCP SDUs corresponding thereto) in abuffer. The PDCP entity 112 may provide the PDCP SDUs from the PDCP PDUscorresponding to the PDCP SNs 11, 12, 13, 17, 18, and 19, which arestored in the buffer to the upper layer after the PDCP entity 112provides the PDCP SDUs from the PDCP PDUs corresponding to the PDCP SNs6, 7, 8, 9, and 10 to an upper layer from the time t32.

FIGS. 4A and 4B are block diagrams illustrating examples of a wirelesscommunication system according to example embodiments of the inventiveconcepts. For example, the block diagrams of FIGS. 4A and 4B illustrateE-UTRA (Evolved-Universal Terrestrial Radio Access)-NR (EN)-DC as anexample of DC and the EN-DC may correspond to option 3 of 5G deployment.In FIGS. 4A and 4B, solid lines may correspond to user planes and dashedlines may correspond to control planes. Hereinafter, descriptionpreviously given with reference to FIGS. 4A and 4B will not be given.

Referring to FIG. 4A, an EPC 30 a as a core network may include amobility management entity (MME) 32 a and a serving gateway (SGW) 34 a.In some example embodiments, the EPC 30 a may further include a homesubscriber server (HSS), which is connected to the MME 32 a, and apacket data network (PDN) gateway (PGW) which is connected to the SGW 34a and a PDN outside the EPC 30 a. An eNB 21 a as the MN may be connectedto the MME 32 a of the EPC 30 a through an S1-C interface, may beconnected to the SGW 34 a of the EPC 30 a through an S1-U interface, andmay be connected to an en-gNB 22 a through an X2-U interface and an X2-Cinterface. In addition, the en-gNB 22 a as the SN may be connected tothe eNB 21 a through the X2-U interface and the X2-C interface. In anexample of FIG. 4A, a bearer split from the eNB 21 a may be generated.

Referring to FIG. 4B, an EPC 30 b may include an MME 32 b and an SGW 34b. An eNB 21 b may be connected to the MME 32 b through the S1-Cinterface, may be connected to the SGW 34 b through the S1-U interface,and may be connected to an en-gNB 22 b through the X2-U interface andthe X2-C interface. In addition, the en-gNB 22 b may be connected to theSGW 34 b through the S1-U interface and may be connected to the eNB 21 bthrough the X2-U interface and the X2-C interface. In an example of FIG.4B, a bearer split from the en-gNB 22 b may be generated.

UEs 10 a and 10 b of FIGS. 4A and 4B may respectively experiencedifferent delays caused by an X2 interface (e.g., the X2-U interface andthe X2-C interface.) as described below with reference to FIGS. 5A and5B. Therefore, sizes of buffers required by the UEs 10 a and 10 b ofFIGS. 4A and 4B may be different from each other and the UEs 10 a and 10b of FIGS. 4A and 4B may not distinguish a configuration of FIG. 4A froma configuration of FIG. 4B in the DC. Therefore, a buffer of a sizedefined by the [EQUATION 1] and the [EQUATION 2] may cause waste ofmemory capacity in accordance with a configuration thereof. Hereinafter,example embodiments of the inventive concepts will be described mainlywith reference to the EN-DC. However, example embodiments of theinventive concepts may also be applied to DC based on a single RAT, forexample, LTE-DC or NR-DC as well as DC based on a multi-RAT (MR) (thatis, MR-DC) such as the EN-DC, for example, NG-RAN E-UTRA-NR (NGEN)-DC orNR-E-UTRA (NE)-DC.

FIGS. 5A and 5B are timing diagrams illustrating examples of a bufferingoperation performed by UE for data reordering in accordance withcomparative examples. For example, the timing diagram of FIG. 5Aillustrates a buffering operation that may be performed for reorderingdata in the UE 10 a of FIG. 4A and the timing diagram of FIG. 5Billustrates a buffering operation that may be performed for reorderingdata in the UE 10 b of FIG. 4B. Hereinafter FIGS. 5A and 5B will bedescribed with reference to FIGS. 4A and 4B and description previouslygiven with reference to FIGS. 5A and 5B will not be given.

Referring to FIG. 5A, the UE 10 a may store data received from the eNB21 a in a buffer during LTE RLC Round-Trip Time (RTT), that is, from atime t51 to a time t54. In addition, the UE 10 a may store data receivedfrom the en-gNB 22 a during NR RLC RTT, that is, from a time t52 to atime t53. As illustrated in FIG. 5A, the time t52 may correspond to apoint in time delayed D51 from the time t51 due to the X2 interfacebetween the eNB 21 a and the en-gNB 22 a. In accordance with Document 1,the LTE RLC RTT may be 75 ms, the NR RLC RTT may be 40 ms whensubcarrier spacing (SCS) is 30 KHz, and a delay D51 may be 25 ms (X2/Xndelay+Queuing in SN=25 ms). Therefore, the UE 10 a may store the datareceived from the eNB 21 a and the en-gNB 22 a for 75 ms total in thebuffer and the buffer may be required to have a size for storing thecorresponding data.

Referring to FIG. 5B, the UE 10 b may store data received from theen-gNB 22 b during the NR RLC RTT, that is, from a time t55 to a timet56. In addition, the UE 10 b may store data received from the eNB 21 bduring the LTE RLC RTT, that is, from a time t57 to a time t58. Asillustrated in FIG. 5B, the time t57 may correspond to a point in timedelayed D52 from the time t55 due to the X2 interface between the eNB 21b and the en-gNB 22 b. In accordance with Document 1, the LTE RLC RTTmay be 75 ms, the NR RLC RTT may be 40 ms when the SCS is 30 KHz, and adelay D52 may be 55 ms (X2/Xn delay+Queuing in MN=55 ms). Therefore, theUE 10 b may store the data received from the eNB 21 b and the en-gNB 22b for 130 ms total (130 ms=55 ms+75 ms) in the buffer and the buffer maybe required to have a size for storing the corresponding data.

As described above, because buffer sizes required by the UEs may bedifferent from each other and a delay caused by the X2/Xn interface mayvary by BS, it may be inefficient for UE to always allocate a memoryregion corresponding to the maximum size of a buffer to reordering ofdata in DC. For example, in a case in which the UE 10 b of FIG. 4Breceives the data from the eNB 21 b at a data rate of 2 Gbps andreceives the data from the en-gNB 22 b at a data rate of 5 Gbps, whenthe delay caused by the X2 interface is 45 ms, a buffer of an additionalsize of 39.375 MB may be required (39.375 MB=28.125 MB+11.25 MB).Therefore, according to example embodiments of the inventive concepts,memory capacity of dozens of MB may be saved.

FIG. 6 is a block diagram illustrating base stations (BS) and UE in DCaccording to example embodiments of the inventive concepts. For example,the block diagram of FIG. 6 illustrates an eNB 21′, an en-gNB 22′, andUE 10′ in the EN-DC. Hereinafter, description previously given withreference to FIG. 6 will not be given.

Referring to FIG. 6, the UE 10′ may include an antenna 12, a transceiver14, at least one processor 16, and/or a memory 18. The antenna 12 mayreceive a radio frequency (RF) signal transmitted by the eNB 21′ and/orthe en-gNB 22′ in a receive (RX) mode and may transmit an RF signalprovided by the transceiver 14 to the eNB 21′ and/or the en-gNB 22′ in atransmit (TX) mode. In some example embodiments, the antenna 12 may beimplemented by an antenna array including a plurality of antennas and/oras a package with the transceiver 14.

The transceiver 14 may generate a baseband (BB) signal by processing anRF signal received from the antenna 12 in the RX mode and may providethe BB signal to the at least one processor 16. In addition, thetransceiver 14 may generate an RF signal by processing the BB signalprovided by the at least one processor 16 in the TX mode and may outputthe RF signal to the antenna 12. In some example embodiments, thetransceiver 14 may include a filter, a mixer, a power amplifier (PA),and a low noise amplifier (LNA) and may be referred to as a radiofrequency integrated circuit (RFIC).

The at least one processor 16 may process the BB signal received fromthe transceiver 14 in the RX mode and may generate the BB signal and mayprovide the BB signal to the transceiver 14 in the TX mode. For example,the at least one processor 16 may include a demodulator, a decoder, anencoder, and a modulator and may perform functions of layers included ina protocol stack. For this purpose, the at least one processor 16 mayinclude a logic block designed by logic synthesis and/or at least onecore configured to execute a series of instructions. The at least oneprocessor 16 may be referred to as a communication processor, a BBprocessor, or a modem and, may be referred to as a first processorherein.

The memory 18 may be accessed by the at least one processor 16, maystore data provided by the at least one processor 16, and may providethe stored data to the at least one processor 16 in response to arequest of the at least one processor 16. The memory 18 may include avolatile memory such as a static random access memory (SRAM) or adynamic random access memory (DRAM) or a non-volatile memory such as aflash memory or a resistive random access memory (RRAM).

The at least one processor 16 may use at least a part of the memory 18as a buffer for DC. For example, the at least one processor 16 mayimplement the PDCP entity 112 of FIG. 2 and the memory 18 may provide abuffer for reordering the PDCP PDUs in the DC. The at least oneprocessor 16 may identify a delay caused by the X2/Xn interface betweenthe eNB 21′ and the en-gNB 22′ and may adjust a size of a buffer basedon the delay caused by the X2/Xn interface. Therefore, a region that isnot allocated as a buffer in the memory 18 may be used for anotherfunction performed by the at least one processor 16 and, as a result,the at least one processor 16 may provide improved functions and theperformance of the UE 10′ may improve. In addition, the capacity of thememory 18 may be reduced so that cost of the UE 10′ may be reduced.

As illustrated in FIG. 6, the eNB 21′ may include an antenna 212, atransceiver 21_4, at least one processor 216, and/or a memory 21_8 likethe UE 10′. The en-gNB 22′ may also include an antenna 22_2, atransceiver 22_4, at least one processor 22_6, and/or a memory 22_8 likethe UE 10′.

FIG. 7 is a flowchart illustrating a method of improving or optimizing abuffer size in DC according to example embodiments of the inventiveconcepts. As illustrated in FIG. 7, the method of improving oroptimizing the buffer size in the DC may include a plurality ofoperations S10, S30, S50, S70, and/or S90. In some example embodiments,the method of FIG. 7 may be performed by the UE 10′, the eNB 21′, and/orthe en-gNB 22′ of FIG. 6. Hereinafter, it is assumed that the method ofFIG. 7 is performed by the UE 10′ of FIG. 6 and the method of FIG. 7will be described with reference to FIG. 6

In operation S10, a delay between a first BS and a second BS may beidentified. For example, the at least one processor 16 of the UE 10′ mayidentify the delay caused by the X2/Xn interface between the eNB 21′ andthe en-gNB 22′. The at least one processor 16 may identify the delaycaused by the X2/Xn interface by various methods, and examples ofoperation S10 will be described below with reference to FIGS. 9A, 9B,10A, and 10B.

In operation S30, the buffer size may be adjusted. For example, the atleast one processor 16 may allocate a partial region of the memory 18 toa buffer to be used for reordering data in the DC. The at least oneprocessor 16 may adjust the buffer size based on the delay identified inoperation S10 instead of allocating an region of the memory 18corresponding to the maximum size of the buffer to the buffer based on afixed delay. Therefore, an region of the memory 18 that is not allocatedto the buffer may be used for other operations. An example of operationS30 will be described with reference to FIG. 8.

In operation S50, first data and second data may be received. Herein,for example, the UE 10′ may receive the first data from the eNB 21′ andmay receive the second data from the en-gNB 22′. The first data and thesecond data may include the PDCP PDUs, and the UE 10′ may receive thenon-sequential PDCP PDUs.

In operation S70, the first data and the second data may be stored inthe buffer. For example, the at least one processor 16 (or the PDCPentity) may store the first data and the second data in the bufferhaving the size adjusted in operation S30, that is, the region allocatedto the buffer in the memory 18 Therefore, the memory 18 may store thePDCP PDUs (or the PDCP SDUs generated thereby).

In operation S90, an RB may be generated. For example, the at least oneprocessor 16 may generate the RB by reordering the first data and thesecond data stored in the buffer. That is, the at least one processor 16(or the PDCP entity) may sequentially provide the PDCP SDUs to an upperlayer by reordering the PDCP PDUs stored in the buffer (or the PDCP SDUsgenerated thereby). In an example embodiment, RB may include PDCP SDUs.

FIG. 8 is a timing diagram illustrating an example of a bufferingoperation performed by UE for data reordering according to exampleembodiments of the inventive concepts. For example, the timing diagramof FIG. 8 illustrates a buffering operation performed by using thebuffer having the size adjusted in operation S30 of FIG. 7. In someexample embodiments, the buffering of FIG. 8 may be performed by the atleast one processor 16 included in the UE 10′ of FIG. 6. Hereinafter,FIG. 8 will be described with reference to FIG. 6.

Referring to FIG. 8, the at least one processor 16 may store the datareceived from the en-gNB 22′ in the region allocated to the buffer inthe memory 18 during the NR RLC RTT, that is, from a time t81 to a timet83. In addition, the at least one processor 16 may store the datareceived from the eNB 21′ in the region allocated to the buffer in thememory 18 during the LTE RLC RTT, that is, from a time t82 to a timet84. The at least one processor 16 may identify a delay D80 between theeNB 21′ and the en-gNB 22′ of FIG. 6 and the delay D80 may be less thanthe delay D52 of FIG. 5B. For example, when the delay D80 is 10 ms (10ms<55 ms), the at least one processor 16 may store the data receivedfrom the eNB 21′ and the en-gNB 22′ for 85 ms total in the buffer and abuffer of a reduced size may be allocated in the memory 18 in order tostore the corresponding data.

FIGS. 9A and 9B are flowcharts illustrating examples of a method ofimproving or optimizing a buffer size in DC according to exampleembodiments of the inventive concepts. For example, the flowcharts ofFIGS. 9A and 9B illustrate examples of an operation of a BS providing ameasured value corresponding to a delay between BSs to UE and the UE mayidentify the delay between the BSs based on the measured value providedby the BS. Hereinafter, description previously given with reference toFIGS. 9A and 9B will not be given.

Referring to FIG. 9A, in operation S01, an eNB 92 a may form DC. Forexample, the eNB 92 a may form the EN-DC with an en-gNB and UE 91 a andmay function as the MN in the EN-DC.

In operation S02, the eNB 92 a may identify the inter-BS delay. Forexample, the eNB 92 a may identify the delay between the eNB 92 a andthe en-gNB. In some example embodiments, the eNB 92 a may measure anX2/Xn delay and may identify at least one of queuing in the eNB 92 a andqueuing in the en-gNB. The eNB 92 a may calculate the delay between theeNB 92 a and the en-gNB based on at least one of the X2/Xn delay, thequeuing in the eNB 92 a and the queuing in the en-gNB. In some exampleembodiments, the eNB 92 a may measure the inter-BS delay. For example,the eNB 92 a may measure the delay between the eNB 92 a and the en-gNBbased on a difference between a point in time at which data is receivedfrom the UE 91 a and a point in time at which data is received from theUE 91 a via the en-gNB during the UL data transmission in the DC. Insome example embodiments, the eNB 92 a may include a memory storing thedelay between the eNB 92 a and the en-gNB instead of measuring the delayand the delay between the eNB 92 a and the en-gNB may be read from thememory.

In operation S03, the eNB 92 a may transmit the measured value to the UE91 a. For example, the eNB 92 a may transmit a value corresponding tothe delay identified in operation S02 and that may be identified by theUE 91 a to the UE 91 a as the measured value. The eNB 92 a may transmitthe measured value to the UE 91 a by using arbitrary methods, forexample, may transmit the measured value to the UE 91 a through anarbitrary message that may be provided from the eNB 92 a to the UE 91 asuch as RRC signaling (for example, an RRC message) or MAC signaling(for example, an MAC control element). In an example embodiment, themeasured value may be included in at least one of RRC signaling and MACsignaling.

In operation S10′, the UE 91 a may identify the delay. For example, theUE 91 a may identify the delay based on the measured value received fromthe eNB 92 a. In some example embodiments, the measured value receivedfrom the eNB 92 a may include an index indicating one of a plurality ofdelays included in a table shared by the eNB 92 a and the UE 91 a mayidentify the delay corresponding to the index in the table. In someexample embodiments, the measured value received from the eNB 92 a mayinclude a value of a variable included in an equation shared by the eNB92 a and the UE 91 a may identify the delay by substituting the measuredvalue for the equation.

Referring to FIG. 9B, in operation S04, UE 91 b may request an eNB 92 bfor the measured value. For example, when handover occurs or it isnecessary to secure an additional memory region, the UE 91 b may requestthe eNB 92 b for the measured value corresponding to a delay between theeNB 92 b and an en-gNB. The UE 91 b may transmit the request through anarbitrary message that may be provided to the eNB 92 b.

In operation S05, the eNB 92 b may transmit the measured value to the UE91 b in response to the request of the UE 91 b. In operation S10″, theUE 91 b may receive the measured value from the eNB 92 b and mayidentify the delay between the eNB 92 b and the en-gNB based on thereceived measured value. In some example embodiments, unlike in FIG. 9B,the UE 91 b may not receive a response for the request from a BS. Insome example embodiments, as described below with reference to FIGS. 10Aand 10B, a delay between BSs may be measured by the UE 91 b. In someexample embodiments, UE 91 b may request the first BS (e.g., eNB 92 b)and the second BS (e.g., en-gNB) for information on the delay (e.g., themeasured value) and, when a response including the information is notreceived, UE 91 b may calculate the delay using the method describedbelow with reference to FIGS. 10A and 10B.

FIGS. 10A and 10B are flowcharts illustrating examples of a method ofimproving or optimizing a buffer size in DC according to exampleembodiments of the inventive concepts. For example, the flowcharts ofFIGS. 10A and 10B illustrate examples of operation S10 of FIG. 7 ofidentifying the delay between the BSs in the DC. In some exampleembodiments, operation S10 a of FIG. 10A and operation S10 b of FIG. 10Bmay be performed by the at least one processor 16 included in the UE 10′of FIG. 6. Hereinafter, FIGS. 10A and 10B will be described withreference to FIG. 6.

Referring to FIG. 10A, operation S10 a may include a plurality ofoperations S11 to S13. In operation S11, a point in time at which firstdata is received may be logged and, in operation S12, a point in time atwhich second data is received may be logged. For example, the at leastone processor 16 may store, in an internal register or the memory 18,the point in time at which the first data is received from the eNB 21′and the point in time at which the second data is received from theen-gNB 22′.

In operation S13, the delay may be calculated from a time difference.For example, the at least one processor 16 may calculate the delaybetween the eNB 21′ and the en-gNB 22′ from the time difference betweenthe point in time at which the first data is received, which is storedin operation S11, and the point in time at which the second data isreceived, which is stored in operation S12.

Referring to FIG. 10B, operation S10 b may include operation S14 andoperation S15. In operation S14, a plurality of time differences may becollected. For example, the at least one processor 16 may calculate aplurality of time differences respectively corresponding to a pluralityof RBs by repeatedly performing operation S11 and operation S12 of FIG.10A and may store the plurality of calculated time differences in thememory 18.

In operation S15, the delay may be calculated based on the plurality ofcollected time differences. For example, the at least one processor 16may read the plurality of time differences from the memory 18 and maystatistically calculate the inter-BS delay from the plurality of timedifferences. When data throughput is high, for example, when a channelstate between the UE 10′ and the eNB 21′ and/or the en-gNB 22′ is good,hybrid automatic repeat request (HARQ) retransmission may hardly occurand variation among the plurality of collected time differences may below. On the other hand, when the channel state between the UE 10′ andthe eNB 21′ and/or the en-gNB 22′ is bad, the variation among theplurality of collected time differences may be high. In some exampleembodiments, the at least one processor 16 may calculate the delay basedon an average among the plurality of time differences.

FIG. 11 is a view illustrating a radio access network (RAN) according toexample embodiments of the inventive concepts. As illustrated in FIG.11, the RAN may include a first BS 41 covering a first cell C1, a secondBS 42 covering a second cell C2, and a third BS 43 covering a third cellC3 and UE may form DC with at least two BSs among the first BS 41, thesecond BS 42, and the third BS 43.

The identification of the inter-BS delay and the adjustment of thebuffer size, which are described above with reference to the drawings,may be performed when handover occurs. That is, operation S10 andoperation S30 of FIG. 7 may be triggered by the handover in the UE. Forexample, the UE may form the DC with the first BS 41 and the second BS42 and may use a buffer having a size adjusted based on a first delayD11 between the first BS 41 and the second BS 42 for the DL datatransmission. As the UE moves from the second cell C2 to the third cellC3, the handover may occur. The UE may identify a second delay D12between the first BS 41 and the third BS 43 in order to form the DC withthe first BS 41 and the third BS 43 and may adjust the buffer size basedon the identified second delay D12. In some example embodiments, asdescribed above with reference to FIGS. 9A and 9B, the UE may receive ameasured value corresponding to the second delay D12 from the first BS41 and/or the third BS 43 when the handover occurs. In addition, in someexample embodiments, as described above with reference to FIGS. 10A and10B, the UE may collect at least one time difference when the handoveroccurs and may calculate the second delay D12 based on the at least onecollected time difference. The UE may reallocate regions of a memory tooperations based on the buffer of the changed size.

FIGS. 12A and 12B are block diagrams illustrating examples of device forwireless communication according to example embodiments of the inventiveconcepts. For example, each of the devices 50 a and 50 b of FIGS. 12Aand 12B may be included in the first BS 21, the second BS 22, and/or theUE 10 of FIG. 1. Hereinafter, in FIGS. 12A and 12B, it is assumed thatthe devices 50 a and 50 b are included in the UE.

Referring to FIG. 12A, the device 50 a may include at least oneprocessor 51 and a memory 52. As described above with reference to thedrawings, the at least one processor 51 may identify the delay betweenthe BSs and may allocate a first region R1 of the memory 52 to the layer2 buffer based on the identified delay. Therefore, the at least oneprocessor 51 may store data in the first region R1 of the memory 52 inorder to reorder data in the DC. The at least one processor 51 mayallocate a second region R2 different from the first region R1 of thememory 52 to data logging. For example, the at least one processor 51may use the second region R2 as at least a part of an region that is notallocated to a buffer, for logging events (or data) generated duringwireless communication with a BS. When a short inter-BS delay ismeasured, the first region R1 may be reduced and the second region R2may increase. Therefore, more events may be logged in the second regionR2 of the memory 52 and, as a result, verification efficiency of thewireless communication system and/or debugging efficiency of the UE 10′may increase.

Referring to FIG. 12B, the device 50 b may include a communicationprocessor 53, an application processor 54, a hardware accelerator 55, amemory 56, and/or a bus 57 and the communication processor 53, theapplication processor 54, the hardware accelerator 55, and/or the memory56 may communicate with one another through the bus 57.

The communication processor 53 may perform operations for the wirelesscommunication with the BS. For example, the communication processor 53may correspond to the at least one processor 16 included in the UE 10′of FIG. 6 and may be referred to as a modem or a BB processor. Thecommunication processor 53 may generate BB data for transmitting dataprovided by the application processor 54 to the BS in a TX mode and mayprovide data generated by processing the BB data received from the BS ina RX mode to the application processor 54. Herein, the communicationprocessor 53 may be referred to as a first processor.

The application processor 54 may control the device 50 b and maycommunicate with the BS or another UE through the communicationprocessor 53. In some example embodiments, the application processor 54may include at least one core executing a series of instructions and mayexecute an operating system (OS) and a plurality of applications on theOS.

The hardware accelerator 55 may refer to a dedicated block designed toperform a specific function. For example, the hardware accelerator 55may be designed in order to perform video encoding and decoding andneural processing at a high speed. The hardware accelerator 55 mayinclude a logic block designed by logic synthesis and/or at least onecore configured to execute a series of instructions. Herein, theapplication processor 54 and/or the hardware accelerator 55 may bereferred to as second processors.

The memory 56 may be shared by at least two among the communicationprocessor 53, the application processor 54, and the hardware accelerator55. For example, as illustrated in FIG. 12B, the communication processor53 may access the memory 56 through the bus 57 and may use the firstregion R1 of the memory 56 as the buffer for reordering the data in theDC. In addition, the application processor 54 and/or the hardwareaccelerator 55 may access the memory 56 through the bus 57 and may use athird region R3 of the memory 56 as a shared region. In an exampleembodiment, the third region R3 may be at least a part of an re gion ofthe memory 56 that is not allocated as a buffer. For example, theapplication processor 54 may store data to be provided to the hardwareaccelerator 55 in the third region R3 of the memory 56 and the hardwareaccelerator 55 may store data to be provided to the applicationprocessor 54 in the third region R3 of the memory 56. As described abovewith reference to the drawings, the communication processor 53 mayidentify the delay between the BSs and may allocate the first region R1of the memory 56 to the layer 2 buffer based on the identified delay.When a short inter-BS delay is measured, the first region R1 may bereduced and the third region R3 may increase. Therefore, a shared regionmay increase in the memory 56 and, as a result, the performance of thedevice 50 b may improve.

One or more of the elements disclosed above may include or beimplemented in one or more processing circuitries such as hardwareincluding logic circuits; a hardware/software combination such as aprocessor executing software; or a combination thereof. For example, theprocessing circuitry more specifically may include, but is not limitedto, a central processing unit (CPU), an arithmetic logic unit (ALU), adigital signal processor, a microcomputer, a field programmable gatearray (FPGA), a System-on-Chip (SoC), a programmable logic unit, amicroprocessor, application-specific integrated circuit (ASIC), etc.

While the inventive concepts have been particularly shown and describedwith reference to example embodiments thereof, it will be understoodthat various changes in form and details may be made therein withoutdeparting from the spirit and scope of the following claims.

1. A device for wireless communication of user equipment (UE) in a dualconnection system, the device comprising: a memory configured to providea buffer storing first data received from a first base station (BS) andsecond data received from a second BS; and a first processor configuredto generate a radio bearer (RB) by reordering the first data and thesecond data and adjust a size of the buffer based on a delay between thefirst BS and the second BS.
 2. The device of claim 1, wherein the firstprocessor is further configured to identify the delay based on ameasured value provided by the first BS.
 3. The device of claim 2,wherein the measured value is included in at least one of radio resourcecontrol (RRC) signaling and medium access control (MAC) signaling. 4.(canceled)
 5. The device of claim 1, wherein the first processor isfurther configured to calculate the delay based on a time differencebetween a point in time at which the first data is received and a pointin time at which the second data is received.
 6. The device of claim 5,wherein the first processor is further configured to calculate the delaybased on a plurality of time differences respectively corresponding to aplurality of RBs.
 7. The device of claim 5, wherein the first data andthe second data comprise packet data convergence protocol (PDCP) packetdata units (PDU), and wherein the RB comprises a PDCP service data unit(SDU). 8.-9. (canceled)
 10. The device of claim 1, wherein the delaycomprises an X2/Xn delay between the first BS and the second BS andcomprises queuing in the first BS or queuing in the second BS.
 11. Thedevice of claim 1, wherein the first processor is further configured touse at least a part of a region of the memory excluding the buffer, fordata logging while performing the wireless communication.
 12. The deviceof claim 1, further comprising: a bus connected to the memory and thefirst processor; and a second processor connected to the bus, whereinthe second processor is configured to use at least a part of a region ofthe memory excluding the buffer.
 13. A method of user equipment (UE) ina dual connection system for wireless communication, the methodcomprising: storing first data received from a first base station (BS)and second data received from a second BS in a first region of a memory,the first region being allocated to a buffer; generating a radio bearer(RB) by reordering the first data and the second data; and adjusting asize of the first region based on a delay between the first BS and thesecond BS.
 14. The method of claim 13, further comprising identifyingthe delay based on a measured value provided by the first BS.
 15. Themethod of claim 13, further comprising calculating the delay based on atime difference between a point in time at which the first data isreceived and a point in time at which the second data is received. 16.The method of claim 15, wherein the calculating of the delay comprises:collecting a plurality of time differences respectively corresponding toa plurality of RBs; and calculating the delay based on the plurality oftime differences.
 17. The method of claim 13, further comprisingallocating a second region of the memory, which is different from thefirst region, to data logging, while performing the wirelesscommunication.
 18. A method performed by a first base station (BS) forwireless communication, the method comprising: forming dual connectivity(DC) with a second BS and user equipment (UE); identifying a delaybetween the first BS and the second BS; and transmitting a measuredvalue corresponding to the identified delay to the UE.
 19. The method ofclaim 18, wherein the identifying of the delay comprises: identifying anX2/Xn delay between the first BS and the second BS; identifying at leastone of queuing in the first BS and queuing in the second BS, the queuingin the second BS being obtained from the second BS; and calculating thedelay between the first BS and the second BS based on at least one ofthe X2/Xn delay, the queuing in the first BS, and the queuing in thesecond BS.
 20. The method of claim 18, wherein the measured value isincluded in at least one of radio resource control (RRC) signaling andmedium access control (MAC) signaling.
 21. The method of claim 18,further comprising: receiving first data from the UE; receiving seconddata from the UE through the second BS; and generating a radio bearer(RB) by reordering the first data and the second data, wherein theidentifying of the delay comprises calculating a delay between the firstBS and the second BS based on a time difference between a point in timeat which the first data is received and a point in time at which thesecond data is received.
 22. The method of claim 18, wherein thetransmitting of the measured value to the UE is performed when handoverof the UE occurs.
 23. The method of claim 18, further comprisingreceiving a request for the measured value from the UE, wherein thetransmitting of the measured value to the UE is performed in response tothe request from the UE.